With the continue increase of the integration level of integrated circuits (ICs), the integration level has gradually reached the upper limitation. Thus, a three-dimensional (3D) IC technology has been developed. The 3D IC is defined as a system level integration structure. The 3D IC realizes the vertical interconnections of a plurality of chips by wafer bonding processes. Thus, the spaces of the chip is increased; and the integration level is increased as well. At the same time, the working speed of the ICs is also increased; and the power consumption is reduced. Currently, the 3D IC technology is one of the most important area in IC design.
3D IC technology often utilizes through silicon vias (TSVs) and the metal interconnect structures above the TSVs to form electrical interconnections; and then the wafer bonding is further realized between two wafers. As one of the key technologies in 3D IC, wafer level Cu—Cu bonding has an important application potential in the high-end products.
However, the bonding performance of the wafer bonding structure is not as expected. Thus, there is a need to further improve the bonding performance of the wafer bonding structures. The disclosed methods and structures are directed to solve one or more problems set forth above and other problems in the art.